The present invention is generally directed to RF transceivers and, in particular, to a low-noise amplifier circuit for use in a RF transceiver.
The power consumption, speed, noise, and distortion characteristics of radio frequency (RF) transceivers are significantly affected by the performance of the RF amplifiers used in the transmit signal path and the receive signal path. If an amplifier has good (or high) linearity, the amount of signal distortion introduced by amplification is minimized and high signal quality is maintained in the presence of larger interfering signals. However, in order to maintain high linearity, an amplifier must be operated at power supply voltages that are much higher that the average peak-to-peak signal voltage. This greatly increases the power consumption of the RF amplifier, resulting in a tradeoff between linear performance and power consumption.
Often it is desirable to switch the gain of a low-noise amplifier (LNA) at the front-end of a receiver to compensate for varying signal conditions at the input of the radio receiver. For instance, for low input signal strength, maximum gain is desired to increase the sensitivity of the receive path. However, if large interfering signals are present along with a medium strength information signal, it may be advantageous to reduce the LNA gain such that the interfering signals do not overload subsequent blocks in the receive path.
Commonly used techniques of adjusting LNA gain have well-known drawbacks. FIG. 2 illustrates selected portions of low-noise amplifier (LNA) 105 in the exemplary RF transceiver according to one embodiment of the prior art. For ease of explanation, DC bias circuits are omitted from the illustrated embodiment. Prior art LNA 105 comprises inductor 205, n-p-n transistor 210, n-p-n transistor 215, and MOS transistor 220. An input signal, IN, is applied to the base of input transistor 215. A DC bias signal, DC, is applied to the base of output transistor 210 to establish a DC bias current through inductor 205. The IN signal is amplified by transistors 215 and 210 to produce the output signal, OUT, at the collector of transistor 210.
Under normal operation, MOS transistor 220 is fixed in an OFF state by gate voltage CONTROL and appears as an open circuit. When the input voltage CONTROL is switched ON to affect a reduced gain state, MOS transistor 220 shunts the input current away from input transistor 215 and straight into output transistor 210. This reduces the gain according to the value of the CONTROL signal applied to the gate of MOS transistor 220. This LNA bypass mode has the twin disadvantages of high noise figure (NF) and poor return loss. High NF degrades system sensitivity and degradation of return loss reduces the effectiveness of any bandpass filter placed in front of low-noise amplifier 205.
Another method of LNA gain adjustment involves placing a variable attenuator after LNA 105. Although this technique allows for constant return loss over various gain states, it suffers from clumsy implementation within the confines of an integrated circuit. This is especially true in a BiCMOS or SiGe process, wherein the attenuator switching devices most likely are large MOS devices having parasitic loading effects that can limit the maximum gain and/or bandwidth of the low-noise amplifier. Furthermore, the switching devices used to change the attenuator range may cause non-linearities, reducing the LNA input intercept, a critical factor in many receive signal paths.
Therefore, there is a need in the art for improved low-noise amplifier devices for use in RF transceivers. In particular, there is a need for a variable gain low-noise amplifier in which the gain may be adjusted without increasing noise figure and degrading return loss. More particularly, there is a need for an improved variable gain low-noise amplifier that is easy to integrate in an integrated circuit without using attenuator switching devices that have large parasitic loading effects.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide an improved variable gain low-noise amplifier. According to an advantageous embodiment of the present invention, the low-noise amplifier comprises: 1) an input transistor having a first ground terminal coupled to ground and an input terminal coupled to an input signal; 2) a first output transistor having a first output terminal coupled to a second output terminal of the input transistor; 3) a first switch capable of turning the first output transistor ON and OFF by selectively coupling an input terminal of the first output transistor to one of: a) a first enabling voltage and b) a first disabling voltage; 4) a second output transistor having a first output terminal coupled to the second output terminal of the input transistor; 5) a second switch capable of turning the second output transistor ON and OFF by selectively coupling an input terminal of the second output transistor to one of: a) a second enabling voltage and b) a second disabling voltage; and 6) an inductor comprising a first inductor terminal coupled to a supply voltage, a second inductor terminal coupled to a second output terminal of the first output transistor, and a first tap point intermediate the first and second inductor terminals coupled to a second output terminal of the second output transistor.
According to one embodiment of the present invention, the input transistor is an n-p-n transistor.
According to another embodiment of the present invention, the first and second output transistors are n-p-n transistors.
According to still another embodiment of the present invention, the input transistor is an n-p-n transistor, the first and second output transistors are n-p-n transistors, and the first and second disabling voltages are ground reference points.
According to yet another embodiment of the present invention, the input transistor is an n-p-n transistor, the first and second output transistors are n-p-n transistors, and the first and second enabling voltages are bias voltages approximately equal to twice the value of a base-emitter voltage of the first and second output transistors.
According to a further embodiment of the present invention, the input transistor is a MOSFET device.
According to a still further embodiment of the present invention, the first and second output transistors are MOSFET devices.
In one embodiment of the present invention, the variable gain low-noise amplifier further comprises: 1) a third output transistor having a first output terminal coupled to the second output terminal of the input transistor; and 2) a third switch capable of turning the third output transistor ON and OFF by selectively coupling an input terminal of the third output transistor to one of: a) the enabling voltage and b) the disabling voltage.
In another embodiment of the present invention, the inductor further comprises a second tap point intermediate the first tap point and the second inductor terminal coupled to a second output terminal of the third output transistor.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.